1. Field of the Disclosure
The present disclosure broadly relates to pad impedance in MOS (Metal Oxide Semiconductor) driver circuits and, more particularly, to an apparatus and method to correct MOS linear region impedance curvature.
2. Brief Description of Related Art
The high speed I/O standards governing data transfers between two high speed electronic devices require a tight control of output impedance of a device driver or buffer circuit in such devices. In modern I/O standards, the output impedance is required to be controlled to a nominal value +/− some percentage error or variation. For example, FIG. 1 illustrates an exemplary pad impedance specification 10 under USB2.0 (Universal Serial Bus version 2.0) for a low impedance driver circuit. An example of a low impedance drive unit is a USB1.1 (Universal Serial Bus version 1.1) buffer circuit within a USB2.0 PHY (Physical Layer) device. The specifications mandated in the chart in FIG. 1 may apply to such USB1.1 buffer circuits. In USB2.0, the output impedance of a driver circuit or buffer unit must be controlled within 45 Ohms +/−10% of tolerance. Therefore, the allowable range of output impedance becomes from 40.5 Ohms to 49.5 Ohms. This allowable range is shown by the shaded portion in FIG. 1. It is observed from FIG. 1 that such impedance control applies over a certain voltage range on a drive circuit output pad (i.e., the voltage range of Vpad shown in FIG. 2 and discussed later hereinbelow.) In case of USB2.0, this voltage range is from 0V to 1.1V. Beyond Vpad=1.1V, the pad impedance (Rpad in equation (1) given hereinbelow) is allowed to increase as seen from the spread of the shaded region in FIG. 1.
The discussion herein uses the terms “pad” or “integrated circuit pad” interchangeably to refer to an electrically conducting junction or outlet for a circuit that is fabricated using a semiconductor fabrication process (e.g., a CMOS fabrication process). The pad for the circuit allows the circuit to be connected to another circuit on the same integrated circuit (IC) chip or to another circuit or device external to the chip containing the circuit with the terminating pad.
FIG. 2 illustrates a general approach to pad impedance control in a MOS driver circuit 12. The MOS driver circuit 12 is fabricated as part of an integrated circuit (IC) and includes an n-channel MOS transistor M1 (14) having its gate terminal 16 connected to a bias voltage Vgs (denoted as a gate-to-source voltage source 17), its source terminal 18 held at a ground potential, and its drain terminal 20 connected to the integrated circuit's or chip's output pad (IC pad) 24 via a series resistor Rs 22—also referred to interchangeably herein as an internal precision resistor, an internal linearizing resistor or an internal termination resistor. The internal linearizing resistor 22 is typically integrally fabricated (i.e., on the same chip) with the MOS transistor 14. As discussed hereinbelow, an external precision resistor (not shown) may also be used instead of the internal one. The voltage present at the output pad (e.g., when another electronic device is connected to the IC containing the driver circuit 12) is denoted by the variable pad voltage source Vpad 26. In the circuit configuration of FIG. 2, the impedance present at the IC pad 24 may be given by the following equation:
                                          R            pad                    =                                                    V                pad                                            I                pad                                      =                                          R                s                            +                              1                                  β                  ⁡                                      (                                                                  V                        gs                                            -                                              V                        T                                            -                                                                        V                          ds                                                2                                                              )                                                                                      ⁢                                  ⁢        where                            (        1        )                                β        =                              (                                          μ                o                                            C                ox                                      )                    ⁢                      (                          W              L                        )                                              (        2        )            It is noted here that equation (1) neglects the effects of channel length modulation, λ. In equation (1), Rs is the internal linearizing resistor 22, Vgs is the gate-to-source voltage 17, VT is the appropriate threshold voltage (for NMOS or PMOS), Vds is the drain-to-source voltage present in the transistor M1, and β is the transconductance of the MOS device 14 (in mA/Volt). As is known in the art, the value of β is as defined in equation (2), in which μ0 is the surface mobility of the channel (holes for p-channel or electrons for n-channel) given in (cm2/volt.second), Cox is the MOS gate capacitance per unit area (in F/cm2), W is MOS device's effective channel width (cm), and L is MOS device's effective channel length (cm).
It is noted that different MOS fabrication technologies may have different values for μ0 and Cox. If μo and Cox are low, then the width-to-length ratio W/L (i.e., the size of the MOS device) needs to be made very large to compensate for the lower μo and Cox values, thereby maintaining the impedance control for Rpad in equation (1). It is further noted that the equations (1) and (2) apply to the MOS transistor M1 in its linear region (i.e., the region between cutoff and saturation) of operation. The linear region of operation of the MOS transistor 14 with an internal linearizing resistor 22 is shown in the two pad or “output” current (Ipad) versus pad or output voltage (Vpad) graphs (the transconductance graphs) 28, 30 in FIG. 2. In the linear region, the curvature of the Ipad-Vpad graph 28 is small with large value of Vgs 17, whereas the curvature of the Ipad-Vpad graph 30 is large with lower values of Vgs 17. This curvature is interchangeably referred to hereinbelow as “MOS linear region impedance curvature,” or “MOS linear region curvature,” “linear region curvature,” or simply “impedance curvature.” It is known that the slope of an Ipad-Vpad curve gives the reciprocal of Rpad. Thus, because of the MOS linear region curvature, the values of Rpad are not the same or controlled for graphs 28 and 30.
Although the series resistor Rs 22 forces the NMOS transistor M1 to be in its linear region, for this technique of impedance (Rpad) control to work, it is usually assumed that Vgs is at its maximum value (e.g., at supply voltage Vdd in an NMOS device) and that the PVT (Process Voltage Temperature) variation of Rs 22 is relatively small (at least with respect to the PVT impedance variation of transistor M1). The gate-to-source voltage Vgs 17 must normally be at its maximum possible value (for transistor M1 linear region operation) to minimize the impedance curvature of transistor M1 (as, for example, in the graph 28 in FIG. 2) because of the changing Vds as the pad voltage Vpad 26 changes (due to, for example, fluctuations in the operating characteristics of another device or circuit stage connected to the MOS driver circuit 12 through the IC pad 24 or presence of a “return wave front” from such device operating as a signal receiving device).
The effect of PVT spread of the internal linearizing resistor Rs 22 may be illustrated in the case of a USB1.1 buffer within a USB2.0 PHY as follows. In a 0.11 μm embedded CMOS fabrication technology, the value of Rs 22 will spread by as much as 45% from its nominal value over PVT. Thus, for example, if the nominal value (at 0° C.) of Rs=28 Ohms, then it will actually PT spread between about 22 Ohms and 35 Ohms. The problem is the lower 22 Ohm limit because it means that, for a 45 Ohm overall impedance requirement (as discussed hereinbefore with reference to FIG. 1), the linear region of MOS transistor M1 (14) has to make up greater than 50% of that total impedance (or 45 Ohms). Such a high impedance requirement from transistor M1 (14) during its linear region of operation may create an impedance curvature of as much as several Ohms over the 1.1V range of the USB2.0 specification (discussed hereinabove with reference to FIG. 1). If one chooses Rs 22 much higher than 28 Ohms, then the dimensions (W/L) of transistor M1 (14) would be unrealistically huge as can be seen from equations (1) and (2). An external precision resistor (not shown) of high value may be used (as discussed hereinbelow) to maintain the smaller size of M1, but there would still be some linear region curvature (in the Ipad-Vpad graph) and also a need for extra pads (for external precision resistor).
A problem with the current precision resistor approach is that many non-analog CMOS fabrication processes do not have precision resistors available. In such processes, it may not be possible to meet a tight impedance specification with the circuit of FIG. 2. In such processes, some additional form of PVT impedance trimming is usually necessary. At present, three basic solutions (or mixtures of them) exist to control pad impedance within a tight percentage spread.
In the first approach, an external series precision resistor Rs (not shown) is used with essentially no PVT variation. The external resistor is not fabricated along with the MOS transistor M1 (14), but rather externally attached to the IC pad 24 in series with transistor M1 when needed. In this configuration, the internal resistor 22 may be absent from the MOS driver circuit 12. If such an external resistor Rs is made large enough, then one can effectively compensate for large PVT variations in the impedance of transistor M1. Unfortunately, there are some disadvantages with this technique: (1) This technique requires external components and increases system cost and component count. (2) This technique may require more I/O pads (e.g., in case of using such technique for a USB1.1 buffer in a USB2.0 PHY device). (3) Even with an external precision resistor, it may not be possible to meet a tight low impedance specification (e.g., under USB2.0 as discussed above with reference to FIG. 1) because of the need to make transistor M1 inordinately large in size (as can be seen from equations (1) and (2) above).
In the second approach, a “digital” (or “discrete”) impedance trimming technique is used. In this technique, transistor M1 (14) may comprise of a number of NMOS “fingers,” the “correct” number of fingers being activated for any given PVT corner. The advantage of this technique is that Vgs 17 can be kept constant, normally at its maximum possible value (e.g., supply voltage Vdd (not shown)), to minimize the curvature in the linear region impedance of transistor M1 (14). However, the disadvantages of this digital calibration technique are: (1) When it is not possible to drive Vgs to a high value (>>Vds(max) in the Vpad region of interest), then the linear region impedance curvature of transistor M1 (14) can still be very significant. When one takes into account comparator offsets and reference voltage offsets (in the trimming circuit realization), then a tight impedance specification may not be realizable. (2) In this technique, a whole replica pad driver is required for comparison with some reference precision resistor (or current derived from such a precision resistor). This is a waste of silicon area, for example, in a USB2.0 PHY device that needs just two impedance controlled IC pads. The addition of an entire third pad for just impedance control may not be desirable. (3) It is not clear under this technique when one needs to update the impedance (i.e., change the number of NMOS “fingers”). Impedance updating may not be done safely during data transmission because it could cause major discontinuities in the rise/fall in voltage/current characteristics of the transmitting pad. This may cause the overall system to fail. Therefore, the impedance needs to be updated at a time when there is no active data transmission (or data reception, if the pad is being used as a termination resistance as, for example, in the USB2.0 HS mode). However, there may be no clear “gap” in the transmission protocol and, hence, choosing such “update gap” may pause an additional problem for the system designer. Such “update gaps” may be defined in the data protocol; however, that is not the case for USB2.0. The USB2.0 system designer may have to spend time and resource to figure out such “safe gaps” during which impedance may be updated.
In the third approach, an “analog” impedance trimming technique is used. This technique essentially solves many of the problems associated with the digital trimming technique described above. The advantage of the analog trimming technique are: (1) A “fraction” or “scaled version” of the pad cell (i.e., a scaled replica pad driver) can be used for impedance trimming. This saves on silicon area. (2) The trimming process is continuous; thus, one does not need a clear “update” gap in the transmission protocol as with the digital solution. However, the disadvantages of the classical analog solution are: (1) Similar to digital trimming, the analog approach trims the pad impedance for one value of Vpad only. This means that the linear region MOS impedance curvature is not trimmed out for a range of Vpad values. (2) The use of a properly-biased, scaled replica pad may require very tight control of voltage and current references because of the existence of MOS linear region impedance curvature. (3) The Vgs of transistor M1 (14) cannot be kept constant, at its maximum possible value, to minimize linear region impedance curvature. With a fixed size for transistor M1, Vgs 17 will be maximized for the slow process corner (slow process, maximum temperature, minimum supply voltage Vdd, largest internal linearizing resistor Rs value) and, thus, the impedance curvature is minimized for this worst case corner only. For the fast process corner (fast process, minimum temperature, maximum Vdd, smallest Rs value), however, the Vgs 17 will have to be much lower than maximum, resulting in the worst linear region impedance curvature (e.g., as shown in graph 30 in FIG. 2). If the PVT change in Rs 22 is large, then the classic analog solution fails to trim pad impedance to within a tight percentage tolerance.
Therefore, it is desirable to devise an analog solution (given its many advantages in terms of, for example, reduced complexity and conservation of silicon area) to trim out the MOS linear region impedance curvature while accommodating PVT spreads in values of internal or external precision resistors. It is further desirable to maintain a linear impedance for a range of Vpad values, while also maintaining the Vgs at its maximum possible value to obtain greater linearity.